Research ArticleOpen AccessGoogle Scholar indexed
Undergraduate Curriculum Development for Digital Integrated Circuit Design
Department of Electronic Science and Technology, Tongji University, Shanghai, China
- 1 Department of Electronic Science and Technology, Tongji University, Shanghai, China
Creative Education·Volume 03 (2012)·Pages 856–858·Published 23 October 2012·DOI10.4236/ce.2012.326128
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Abstract
This article describes the development of a Digital Integrated Circuit Design curriculum, which includes how to select the design level and how to implement the design. The curriculum is for the undergraduates in grade four, whose major is microelectronics. The development is in the background of very large scale integrated circuits. Since the popular design flow is a hierarchy of abstraction levels, the goal of the curriculum is to develop the students’ ability to design an actual circuit from scratch. Comparison is provided from two aspects. The first aspect is the contents of various published textbooks. The second aspect is the contents of similar courses in famous universities.
KeywordsDigital Integrated CircuitDesign Abstraction LevelTransistor LevelGate LevelHardware Description Language
- Alon, E. (2012) UBC ECE courses. URL (last checked 26 August 2012). http://www.ece.ubc.ca/courses
- Eriksson, H., Larsson-Edefors, P., Henriksson, T. et al. (2003). Full-custom vs. standard-cell design flow—An adder case study. In Proceedings of the ASP-DAC: Asia and South Pacific (pp. 507-510). Kitakyushu: IEEE Publications.
- Fey, C. F., & Paraskevopoulos, D. E. (1989). Studies in VLSI technology economics. IV: Models for gate array design productivity. IEEE Journal of Solid-State Circuits, 24, 1085-1091.
- Kaeslin, H. (2008). Chapter 8: Gate- and transistor-level design. In The digital integrated circuit design: From VLSI architectures to CMOS fabrication (pp. 386-458). Cambridge: Cambridge University Press.
- Karris, S. T. (2007). Chapter 11: Introduction to field programmable devices. In The digital circuit analysis and design with simulink modeling: An introduction to CPLDs and FPGAs. Newton Abbot: Orchard Publications.
- Kriete, R. A., & Mettleton. R. K. (1984). A VLSI design methodology based on parametric macro cells. In Proceedings of 21st design automation conference (pp. 685-687). Piscataway, NJ: IEEE Publications. doi:10.1109/DAC.1984.1585882
- Lai, M. C., Guo, J. J., Zhang, Z. X., & Wang, Z. Y. (2008). Using an automated approach to explore and design a high-efficiency processor element for the multimedia domain. In Proceedings of international conference on complex, intelligent and software intensive systems (pp. 613-618). Los Alamitos, CA: IEEE Publications. doi:10.1109/CISIS.2008.50
- Lemieux, G., & Mehrabadi, R. (2012) UC Berkeley EECS courses. URL (last checked 26 August 2012). http://www-inst.eecs.berkeley.edu/classes-eecs.html
- Li, L. L. (2012). The design and implementation of 90 nm dual-access low power SRAM. Master of Engineering Thesis, Shanghai: Tongji University
- Nelson, B. (2008). Invited talk: FPGA design productivity, a discussion of the state of the art and a research agenda. In Proceedings of international conference on ICECE technology (p. Ixvii). Dhaka: IEEE Publications.
- Purohit, S. et al. (2009) New performance/power/area efficient, reliable full adder design. Proceedings of GLSVLSI. Boston, MA: ACM Press, 493-498. doi:10.1145/1531542.1531654
- Rabaey, J. M., Chandrakasan, A. P., & Nilolic, B. (2003). Part 2: A Circuit Perspective. In The digital integrated circuits: A design perspective (pp. 177-374). Beijing: Pearson Education.