Research ArticleOpen AccessGoogle Scholar indexed
Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation
School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil
School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil
Eldorado Research Institute, Campinas, Brazil
Eldorado Research Institute, Campinas, Brazil
School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil
- 1 School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil
- 2 School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil
- 3 Eldorado Research Institute, Campinas, Brazil
- 4 Eldorado Research Institute, Campinas, Brazil
- 5 School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil
Circuits and Systems·Volume 14 (2023)·Pages 19–28·Published 23 October 2023·DOI10.4236/cs.2023.146003
Copy link · social · email
Abstract
This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V DD = 1.8 V, the resulting set of performance parameters include power consumption P DC = 4.68 mW and phase noise PN @ 1MHz = -107.8 dBc/Hz. From the trade-off involving P DC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.
KeywordsPhase Locked Loop (PLL)Voltage-Controlled Ring Oscillators (VCRO)Dual-Delay-Path DDPDelay Cells
- Jovanovic, G., Stojcev, M. and Stamenkovic, Z. (2010) A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability. Scientific Publications of the State University of Novi Pazar, 2, 1-9.
- Park, C.-H., Kim, O. and Kim, B. (2001) A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching. IEEE Journal of Solid-State Circuits, 36, 777-783. https://doi.org/10.1109/4.918915
- Sun, L.Z. and Kwasniewski, T.A. (2001) A 1.25-GHz 0.35 μm Monolithic CMOS PLL Based on a Multiphase Ring Oscillator. IEEE Journal of Solid-State Circuits, 36, 910-916. https://doi.org/10.1109/4.924853
- Savoj, B. and Razavi, B. (2001) A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector. IEEE Journal of Solid-State Circuits, 36, 761-768. https://doi.org/10.1109/4.918913
- Yang, C.-K.K., Farjad-Rad, R. and Horowitz, M.A. (1998) A 0.5-μm CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling. IEEE Journal of Solid-State Circuits, 33, 713-722. https://doi.org/10.1109/4.668986
- Alioto, M. and Palumbo G. (2001) Oscillation Frequency in CML and ESCL Ring Oscillators. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 48, 210-214. https://doi.org/10.1109/81.904885
- Razavi, B. (1997) Oscillation Frequency in CML and ESCL Ring Oscillators. IEEE Journal of Solid-State Circuits, 32, 730-735. https://doi.org/10.1109/4.568843
- Tomar, A. and Pokharel, R. K. and Nizhnik, O. and Kanaya, H. and Yoshida, K. (2007) Design of 1.1 GHz Highly Linear Digitally-Controlled Ring Oscillator with Wide Tuning Range. IEEE International Workshop on Radio-Frequency Integration Technology, Singapore, 9-11 December 2007, 82-85. https://doi.org/10.1109/RFIT.2007.4443926
- Betancourt-Zamora R.J. and Lee, T.H. (1998) CMOS VCOs for Frequency Synthesis in Wireless Biotelemetry. International Symposium on Low Power Electronics and Design, Monterey, 10-12 August 1998, 91-94. https://doi.org/10.1145/280756.280798
- Jalil J., Reaz, M.B.I., Rahman, L.F., Marufuzzaman, M. and Amin, M.S. (2012) A 2.45 GHz CMOS Voltage Controlled Oscillator for Active Transponder. International Conference on Advances in Circuits, Electronics and Micro-Electronics, 19-24 August 2012, Rome, 1-4.
- Liu, H.Q., Siek, L., Goh, W.L. and Lim, W.M. (2008) A 7-GHz Multiloop Ring Oscillator in 0.18-μm CMOS Technology. Analog Integrated Circuits and Signal Processing, 56, 179-184. https://doi.org/10.1007/s10470-008-9163-z