Basic CMOS VLSI Circuits and Low Power Devices Employing Various Reduction Techniques to Reduce Leakage Power at Low Supply Voltage in Nanoscale Technology — Oak Academic Publishing
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Basic CMOS VLSI Circuits and Low Power Devices Employing Various Reduction Techniques to Reduce Leakage Power at Low Supply Voltage in Nanoscale Technology
School of Electronics and Communication Engineering, Shri Mata Vaishno Devi University, Katra, India
1 School of Electronics and Communication Engineering, Shri Mata Vaishno Devi University, Katra, India
In this work, the author proposed various techniques for reducing leakage power, leakage current, power consumption and power supply voltage. In this work, we implement CMOS Inverter, NAND Gate, CMOS VLSI Based AOI-OAI Circuits and Full Adder. We also compare all implemented circuits with LECTOR Technique and LECTOR Stack State techniques, which are inserted between pull-up and pull-down network Proposed technique simulation has been performed using HSPICE software in 32 nm, 45 nm, 90 nm, and 180 nm nanometer technology with a supply voltage range of 0.6 V - 1.0 V. The battery life of modern mobile computing, multimedia, wireless communication, and other real-time applications is increasing with LECTOR and LECTOR stack state reduction (LSSR). According to HSPICE simulated results by CMOS Inverter, NAND gate, CMOS VLSI Based AOI-OAI circuits and full adder circuits, subthreshold leakage current is decreased by 89% compared to the base case, 80% compared to LECTOR, and 34% compared to LECTOR Stack state reduction method and LECTOR transistor. We can achieve better leakage reduction by controlling supply voltage and by making the switching CMOS transistor.
KeywordsCMOSSubthreshold Leakage CurrentLeakage Control TransistorLECTOR Stack State Reduction
Ramana, S.V. and Rao, P.V.S. (2026) Leakage Power Reduction through Hybrid Mul-ti-Threshold CMOS Stack Technique. International Journal of Engineering & Ex - tended Technologies Research , 8, 3059-3066.
Kishore, D., Chakraborty, S., Biswas, A. and Dumka, A. (2026) Circuit-Level Leakage Reduction Techniques in CMOS Sense Amplifiers for SRAM and TCAM: A Review. Analog Integrated Circuits and Signal Processing , 126, Article No. 37. https://doi.org/10.1007/s10470-026-02562-w
Sun, Y.J. (2026) Research Progress on CMOS Leakage Current Optimization and Low-Power Design. Academic Journal of Science and Technology , 20, 411-418. https://doi.org/10.54097/6hfpvg60
Wang, L. (2024) Recent Advances in Leakage Current Suppression Techniques for Three-Level Inverters. Applied and Computational Engineering , 62, 315-323. https://doi.org/10.54254/2755-2721/62/20240453
Bose, A.P. and Santhi, N. (2024) Efficient Leakage Reduction Approach for Low Power VLSI Design Using Modified Feedback Sleeper Stack Technique. International Journal of Electronics and Communication Engineering , 11, IJECE-V11I3P101. https://doi.org/10.14445/23488549/IJECE-V11I3P101
Deng, L., Li, K. and Shan, W. (2023) IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits. 2023 IEEE In ternational Symposium on Circuits and Systems ( ISCAS ), Monterey, 21-25 May 2023, 1-5. https://doi.org/10.1109/iscas46773.2023.10182138
Moradinezhad Maryan, M., Azhari, S.J. and Amini-Valashani, M. (2022) A Self-Control Leakage-Suppression Block for Low-Power High-Efficient Static Logic Circuit Design in 22 nm CMOS Process. Integration , 87, 1-10. https://doi.org/10.1016/j.vlsi.2022.05.006
Kumar, T.S. and Tripathi, S.L. (2020) Leakage Reduction in 18 nm FinFET Based 7T SRAM Cell Using Self Controllable Voltage Level Technique. Wireless Personal Communications , 116, 1837-1847. https://doi.org/10.1007/s11277-020-07765-6
Kilani, D., Mohammad, B., Alhawari, M., Saleh, H. and Ismail, M. (2019) Analysis and Characterization of Leakage Reduction Methodologies for Stacking, Body Biasing and DLS in 65 nm CMOS Technology. Analog Integrated Circuits and Signal Processing , 102, 1-8. https://doi.org/10.1007/s10470-019-01520-z
Sharma, V.K. (2021) A Survey on Low Power Design Approaches in Nanoscale Regime. Micro and Nanosystems, 13, 129-145. https://doi.org/10.2174/1876402912999200623120558
Karimi, A., Rezai, A. and Hajhashemkhani, M.M. (2018) A Novel Design for Ultra-Low Power Pulse-Triggered D-Flip-Flop with Optimized Leakage Power. Integration , 60, 160-166. https://doi.org/10.1016/j.vlsi.2017.09.002
Lorenzo, R. and Chaudhury, S. (2017) Review of Circuit Level Leakage Minimization Techniques in CMOS VLSI Circuits. IETE Technical Review , 34, 165-187. https://doi.org/10.1080/02564602.2016.1162116
Kumar, P. and Sharma, R.K. (2016) Low Voltage High Performance Hybrid Full Adder. Engineering Science and Technology , an International Journal , 19, 559-565. https://doi.org/10.1016/j.jestch.2015.10.001
Taco, R., Levi, I., Lanuzza, M. and Fish, A. (2016) Low Voltage Logic Circuits Exploiting Gate Level Dynamic Body Biasing in 28 nm UTBB FD-SOI. Solid - State Electronics , 117, 185-192. https://doi.org/10.1016/j.sse.2015.11.013
Rani, V.L. and Latha, M.M. (2016) Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits. Circuits , Systems , and Signal Processing , 35, 4139-4152. https://doi.org/10.1007/s00034-016-0257-z
Gangele, M. and Patra, K.P. (2015) Reduction of Leakage Power in CMOS Circuits Using Stack Technique. International Journal of Modern Engineering Research , 5, 1-8.
Dobriyal, P., Sharma, K., Sethi, M. and Sharma, G. (2013). A High Performance D-Flip Flop Design with Low Power Clocking System Using MTCMOS Technique. 2013 3 rd IEEE International Advance Computing Conference ( IACC ), Ghaziabad, 22-23 February 2013, 1524-1528. https://doi.org/10.1109/iadcc.2013.6514453
Akashe, S. and Sharma, S. (2012) Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology. Wireless Personal Communications , 71, 123-136. https://doi.org/10.1007/s11277-012-0805-1
Verma, P. and Mishra, R.A. (2011) Leakage Power and Delay Analysis of LECTOR Based CMOS Circuits. 2011 2 nd International Conference on Computer and Communication Technology ( ICCCT -2011), Allahabad, 15-17 September 2011, 260-264. https://doi.org/10.1109/iccct.2011.6075117
Deepaksubramanyan, B.S. and Nunez, A. (2007) Analysis of Subthreshold Leakage Reduction in CMOS Digital Circuits. 2007 50 th Midwest Symposium on Circuits and Systems , Montreal, 5-8 August 2007, 1400-1404. https://doi.org/10.1109/mwscas.2007.4488809
Kim, S.H. and Mooney, V.J. (2006) Sleepy Keeper: A New Approach to Low-Leakage Power VLSI Design. 2006 IFIP International Conference on Very Large Scale Integration , Nice, 16-18 October 2006, 367-37. https://doi.org/10.1109/vlsisoc.2006.313263
Hanchate, N. and Ranganathan, N. (2004) LECTOR: A Technique for Leakage Reduction in CMOS Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 12, 196-205. https://doi.org/10.1109/tvlsi.2003.821547
Roy, K., Mukhopadhyay, S. and Mahmoodi-Meimand, H. (2003) Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proceedings of the IEEE , 91, 305-327. https://doi.org/10.1109/jproc.2002.808156
Johnson, M.C., Somasekhar, D., Chiou, L.-Y. and Roy, K. (2002) Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 10, 1-5. https://doi.org/10.1109/92.988724
Powell, M., Yang, S.-H., Falsafi, B., Roy, K. and Vijaykumar, T.N. (2000) Gated-V/sub dd/: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. ISLPED ’00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design , Rapallo, 26-27 July 2000, 90-95. https://doi.org/10.1109/lpe.2000.876763
Kawaguchi, H., Nose, K. and Sakurai, T. (2000) A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current. IEEE Journal of Solid - State Circuits , 35, 1498-1501. https://doi.org/10.1109/4.871328