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A New Approach to Complex Bandpass Sigma Delta Modulator Design for GPS/Galileo Receiver
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Abstract
In this paper, new complex band pass filter architecture for continuous time complex band pass sigma delta modulator is presented. In continuation of paper the modulator is designed for GPS and Galileo receiver. This modulator was simulated in standard 0.18 μm CMOS TSMC technology and has bandwidth of 2MHz and 4MHz for GPS and Galileo centered in 4.092 MHz. The dynamic range (DR) is 56.5/49 dB (GPS/Galileo) at sampling rate of 125 MHz. The modulator has power consumption of 4.1 mw with 3 V supply voltage.
KeywordsContinuous TimeQuadratureSigma DeltaMOSModulatorOTA
- E. D. Gioia and H. Klar, “A 11-bit, 12.5 MHz, Low Power Low Voltage Continuous-Time Sigma-Delta Modulator,” Proceedings of the 17th International Conference on Mixed Design of Integrated on Circuits and Systems (MIXDES), Warsaw, 24-26 June 2010, pp. 176-181.
- G. Mitteregger, C. Ebner, C. Mechnig, T. Blon, C. Holuigue, E. Romani, A. Melodia and V. Melini, “A 14b 20 mW 640 MHz CMOS CT/spl Delta//spl Sigma/ADC with 20 MHz Signal Bandwidth and 12b ENOB,” Solid-State Circuits Conference (ISSCC), Digest of Technical Papers IEEE International, San Francisco, 6-9 February 2006, pp. 131-140.
- E. Prefasi, L. Hernandez, S. Paton, A. Wiesbauer, R. Gaggl and E. Pun, “A 0.1 mm, Wide Bandwidth Continuous-Time ADC Based on a Time Encoding Quantizer in 0.13 m CMOS,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 10, 2009, pp. 2745-2754. doi:10.1109/JSSC.2009.2027550
- S. B. Kim, S. Joeres, N. Zimmermann, M. Robens, R. Wunderlich and S. Heinen, “Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GPS/Galileo Low-IF Receiver,” IEEE International Workshop on Radio-Frequency Integration Technology (RFIT 007), Rasa Sentosa Resort, 9-11 December 2007, pp. 127-130. doi:10.1109/RFIT.2007.4443935
- J. Arias, P. Kiss, V. Prodanov, V. Boccuzzi, M. Banu, D. Bisbal, J.S. Pablo, L. Quintanilla and J. Barbolla, “A 32-mW 320-MHz Continuous-Time Complex Delta- Sigma ADC for Multi-Mode Wireless-LAN Receivers,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 2, 2006, pp. 339-351. doi:10.1109/JSSC.2005.862346
- F. Esfahani, P. Basedau, R. Ryter and R. Becker, “A Fourth Order Continuous-Time Complex Sigma-Delta ADC for Low-IF GSM and EDGE Receivers, in VLSI Circuits,” Symposium on Digest of Technical Papers, 12-14 June 2003, pp. 75-78.
- M. Ortmanns, F. Gerfers and Y. Manoli, “A Continuous-Time Sigma-Delta Modulator with Switched Capacitor Controlled Current Mode Feedback,” Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC’ 03), 16-18 September 2003, pp. 249-252.
- K. Tanno, H. Tanaka, R. Miwa and H. Tamura, “Wide-Common-Mode-Range and High-CMRR CMOS OTA Operable in Both Weak and Strong Inversion Regions,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Macao, 30 November-3 December 2008, pp. 1180-1183.
- S. B. Kim, S. Joeres and S. Heinen, “A Compensation Method of the Excess Loop Delay in Continuous-Time Complex Sigma-Delta Modulators,” 18th European Conference on Circuit Theory and Design (ECCTD), Seville, 27-30 August 2007, pp. 140-143. doi:10.1109/ECCTD.2007.4529556