Research ArticleOpen AccessGoogle Scholar indexed
Analytical and Numerical Model Confrontation for Transfer Impedance Extraction in Three-Dimensional Radio Frequency Circuits
R3 Logic Inc., Monbonnot-Saint-Martin, France
Université de Lyon, Villeurbanne, France
Université de Lyon, Villeurbanne, France
Faculty of Engineering-Ain Shams University, Cairo, Egypt
Université de Lyon, Villeurbanne, France
Université de Lyon, Villeurbanne, France
- 1 R3 Logic Inc., Monbonnot-Saint-Martin, France
- 2 Université de Lyon, Villeurbanne, France
- 3 Université de Lyon, Villeurbanne, France
- 4 Faculty of Engineering-Ain Shams University, Cairo, Egypt
- 5 Université de Lyon, Villeurbanne, France
- 6 Université de Lyon, Villeurbanne, France
Circuits and Systems·Volume 03 (2012)·Pages 126–135·Published 19 April 2012·DOI10.4236/cs.2012.32017
Copy link · social · email
Abstract
3D chip stacking is considered known to overcome conventional 2D-IC issues, using through silicon vias to ensure vertical signal transmission. From any point source, embedded or not, we calculate the impedance spread out; our ultimate goal will to study substrate noise via impedance field method. For this, our approach is twofold: a compact Green function or a Transmission Line Model over a multi-layered substrate is derived by solving Poisson’s equation analytically. The Discrete Cosine Transform (DCT) and its variations are used for rapid evaluation. Using this technique, the substrate coupling and loss in IC’s can be analyzed. We implement our algorithm in MATLAB; it permits to extract impedances between any pair of embedded contacts. Comparisons are performed using finite element methods.
KeywordsThrough Silicon Via (TSV)Green’s FunctionTransmission Line ModelRadio Frequency (RF)Transfer Impedance Extraction
- L. Cadix, C. Bermond, C. Fuchs, A. Farcy, P. Leduc, L. DiCioccio, M. Assous, M. Rousseau, F. Lorut, L. L. Chapelon, B. Flechet, N. Sillon and P. Ancey, “RF Characterization and Modelling of High Density Through Silicon Vias for 3D Chip Stacking,” Microelectronic Engineering, Vol. 87, No. 3, 2010, pp. 491-495. doi:10.1016/j.mee.2009.08.026
- R. Gharpurey and S. Hosur, “Transform Domain Techniques for Efficient Extraction of Substrate Parasitics,” International Conference on Computer-Aided Design, San Jose, 9-13 November 1997, pp. 461-467. doi:10.1109/ICCAD.1997.643576
- P. S. Crovetti and F. L. Fiori, “Efficient BEM-Based Substrate Network Extraction in Silicon SoCs,” Microelectron Journal, Vol. 39, No. 12, 2008, pp. 1774-1784. doi:10.1016/j.mejo.2008.07.034
- M. Abouelatta-Ebrahim, R. Dahmani, O. Valorge, F. Calmon and C. Gontrand, “Modelling of through Silicon via and Devices Electromagnetic Coupling,” Microelectronics Journal, Vol. 42, No. 2, 2011, pp. 316-324 doi:10.1016/j.mejo.2010.10.017
- W8511BP IC-CAP Wafer Professional Measurement Bundle, Agilent.
- COMSOL Multiphysics. http://www.comsol.com/
- R. Gharpurey and R. G. Meyer, “Modeling and Analysis of Substrate Coupling in Integrated Circuits,” IEEE Journal of Solid State Circuits, Vol. 31, No. 3, 1996, pp. 344-353. doi:10.1109/4.494196
- A. M. Niknejad, R. Gharpurey and R. G. Meyer, “Numerically Stable Green Function for Modeling and Analysis of Substrate Coupling in Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 4, 1998, pp. 305-315. doi:10.1109/43.703820
- N. Verghese, D. J. Allstot and S. Masui, “Rapid Simulation of Substrate Coupling Effects in Mixed-Mode ICs,” IEEE Custom Integrated Circuits Conference, San Diego, 9-12 May 1993, pp. 18.3.1-18.3.4. doi:10.1109/CICC.1993.590746
- N. K. Verghese, D. J. Allstot and M. A. Wolfe, “Fast Parasitic Extraction for Substrate Coupling in Mixed-Signal ICs,” IEEE Custom Integrated Circuits Conference, Santa Clara, 1-4 May 1995, pp. 121-124. doi:10.1109/CICC.1995.518149
- Matlab. http://www.mathworks.com/
- C. Gontrand, S. Labiod, O. Valorge, P. Mary, J. C. N. Perez, P. J. Viverge, F. Calmon and S. Latreche, “Markov Chain Approach of Digital Flow Disturbances on Supplies via Heterogeneous Integrated Circuit Substrate,” International Journal of Numerical Modeling, Vol. 30, No. 4, 2010, pp. 54-63. doi:10.2316/Journal.205.2010.2.205-4999.