Research ArticleOpen AccessGoogle Scholar indexed
A Parallel Circuit Simulator for Iterative Power Grids Optimization System
Department of VLSI System Design, Ritsumeikan University, Kusatsu, Japan
Department of Information Engineering, Meijo University, Nagoya, Japan
Department of VLSI System Design, Ritsumeikan University, Kusatsu, Japan
- 1 Department of VLSI System Design, Ritsumeikan University, Kusatsu, Japan
- 2 Department of Information Engineering, Meijo University, Nagoya, Japan
- 3 Department of VLSI System Design, Ritsumeikan University, Kusatsu, Japan
Circuits and Systems·Volume 03 (2012)·Pages 153–160·Published 19 April 2012·DOI10.4236/cs.2012.32020
Copy link · social · email
Abstract
This paper discusses a high efficient parallel circuit simulator for iterative power grid optimization. The simulator is implemented by FPGA. We focus particularly on the following points: 1) Selection of the analysis method for power grid optimization, the proposed simulator introduces hardware-oriented fixed point arithmetic instead of floating point arithmetic. It accomplishes the high accuracy by selecting appropriate time step of the simulation; 2) The simulator achieves high speed simulation by developing dedicated hardware and adopting parallel processing. Experiments prove that the proposed simulator using 80 MHz FPGA and eight parallel processing achieves 35 times faster simulation than software processing with 2.8 GHz CPU while maintaining almost same accuracy in comparison with SPICE simulation.
KeywordsDedicated Hardware AcceleratorPower Grids OptimizationParallel Circuit Simulator
- D. A. Andersson, L. J. Svensson and P. Lasson-Edefors, “Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach,” Proceedings of International Symposium on Quality Electronic Design, San Jose, 17-19 March 2008, pp. 663-669.
- S. W. Wu and Y. W. Chang, “Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology,” Proceedings of Design Automation Conference, San Diego, 7-11 June 2004, pp. 177-180.
- A. Muramatsu, M. Hashimoto and H. Onodera, “Effects of On-Chip Inductance on Power Distribution Grid,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No. 12, 2005, pp. 3564-3572.
- Y. Zhong and M. D. F. Wong, “Thermal-Aware IR Drop Analysis in Large Power Grid,” Proceedings of International Symposium on Quality Electronic Design, San Jose, 17-19 March 2008, pp. 194-199.
- B. Yu and M. L. Bushnell, “Power Grid Analysis of Dynamic Power Cutoff Technology,” Proceedings of International Symposium on Circuits and Systems, New Orleans, 27-30 May 2007, pp. 1393-1396.
- C. Mizuta, J. Iwai, K. Machida, T. Kage and H. Matsuda, “Large-Scale Linear Circuit Simulation with an Inversed Inductance Matrix,” Proceedings of Asia and South Pacific Design Automation Conference, Kanagawa, 27-30 January 2004, pp. 511-516.
- P. M. Lee, S. Ito, T. Hashimoto, J. Sato, T. Touma and G. Yokomizo, “A Parallel and Accelerated Circuit Simulator with Precise Accuracy,” Proceedings of International Conference on VLSI Design, Bangalore, 7-11 August 2002, pp. 213-218.
- N. Nakasato and T. Hamada, “Acceleration of Hydrosynamical Simulations Using a FPGA Board,” Institute of Electronics, Information and Communication Engineers Technical Report, Vol. 105, No. 515, 2006, pp. 19-24.
- T. Watanabe, Y. Tanji, H. Kubota and H. Asai, “Parallel-Distributed Time-Domain Circuit Simulation of Power Distribution Networks with Frequency-Dependent Parameters,” Proceedings of Asia and South Pacific Conference on Design Automation, Yokohama, 24-27 January 2006, pp. 832-837.
- Y. Gu, T. VanCourt and M. C. Herbordt, “Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations,” Proceedings of International Conference of Field Programmable Logic and Applications, Madrid, 28-30 August 2006, pp. 1-8. doi:10.1109/FPL.2006.311190
- L. Zhuo and V. K. Prasanna, “High-Performance and Parameterized Matrix Factorization on FPGAs,” Proceedings of International Conference of Field Programmable Logic and Applications, Madrid, 28-30 August 2006, pp. 363-368. doi:10.1109/FPL.2006.311238