Effect of Temperature & Supply Voltage Variation on Stability of 9T SRAM Cell at 45 nm Technology for Various Process Corners
- 1 VLSI Group, Atal Bihari Vajpayee Indian Institute of Information Technology and Management, Gwalior, India
- 2 Department of Electronics & Communications, Sir Padampat Singhania University, Udaipur, India
- 3 Department of Electronics & Communications, Bipin Chandra Tripathi kumaon Engineering College, Dwarahat, India
Abstract
Due to the continuous rising demand of handheld devices like iPods, mobile, tablets; specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.
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