Research ArticleOpen AccessGoogle Scholar indexed
A Reconfigurable Network-on-Chip Datapath for Application Specific Computing
Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, USA
Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, USA
- 1 Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, USA
- 2 Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, USA
Circuits and Systems·Volume 04 (2013)·Pages 181–192·Published 17 April 2013·DOI10.4236/cs.2013.42025
Copy link · social · email
Abstract
This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.
KeywordsReconfigurable ComputingNetwork-on-ChipNetwork SimulatorsPolymorphic Computing
- “International Technology Roadmap for Semiconductors,” 2009. http://www.itrs.net/Links/2009ITRS/Home2009.htm
- D. Hentrich, E. Oruklu and J. Saniie, “Polymorphic Computing: Definition, Trends, and a New Agent-Based Architecture,” Circuits and Systems, Vol. 2, No. 4, 2011, pp. 358-364. doi:10.4236/cs.2011.24049
- J. Weber, E. Oruklu and J. Saniie, “Architectural Topologies for NoC Datapath Polymorphic Processors,” IEEE International Conference on Electro/Information Technology, Mankato, 15-17 May 2011, pp. 1-6.
- K. Compton and S. Hauck, “Reconfigurable Computing: A Survey of Systems and Software,” ACM Computing Surveys, Vol. 34, No. 2, 2002, pp. 171-210. doi:10.1145/508352.508353
- Z. Guo, W. Najjar, F. Vahid and K. Vissers, “A Quantitative Analysis of the Speedup Factors of FPGAs over Processors,” FPGA Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, New York, 2004, pp. 162-170.
- K. Underwood, “FPGAs vs CPUs: Trends in Peak Floating-Point Performance,” FPGA Proceedings of the ACM/ SIGDA 12th International Symposium on Field Programmable Gate Arrays, New York, 2004, pp. 171-180.
- T. Todman, G. Constantinides, S. Wilton, O. Mencer, W. Luk and P. Cheung, “Reconfigurable Computing: Architectures and Design Methods,” IEEE Proceedings of Computers and Digital Techniques, Vol. 152, No. 2, 2005, pp. 193-207.
- R. Cheung, N. Telle, W. Luk and P. Cheung, “Customizable Elliptic Curve Cryptosystems,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 13, No. 9, 2005, pp. 1048-1059.
- P. Baglietto, M. Maresca and M. Migliardi, “Euclidean Distance Transform on Polymorphic Processor Array,” CAMP Proceedings of Computer Architectures for Ma chine Perception, Como, 18-20 September 1995, pp. 288-293.
- G. Kuzmanov and W. van Oijen, “Floating-Point Matrix Multiplication in a Polymorphic Processor,” ICFPT In ternational Conference on Field-Programmable Technology, Kitakyushu, 12-15 December 2007, pp. 249-252.
- S. Chai, S. Chiricescu, R. Essick, B. Lucas, P. May, K. Moat, J. Norris, M. Schuette and A. Lopez-Lagunas, “Streaming Processors for Next Generation Mobile Imaging Applications,” Communications Magazine, Vol. 43, No. 12, 2005, pp. 81-89. doi:10.1109/MCOM.2005.1561924
- H. Hubert and B. Stabernack, “Profiling-Based Hardware/ Software Coexploration for the Design of Video Coding Architectures,” IEEE Transactions on Circuits and Sys tems for Video Technology, Vol. 19, No. 11, 2009, pp. 1680-1691. doi:10.1109/TCSVT.2009.2031522