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Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits
Faculty of Engineering, Cairo University, Giza, Egypt
Faculty of Engineering, Cairo University, Giza, Egypt
College of Computing and Information Technology, Arab Academy for Science, Technology & Maritime Transport, Cairo, Egypt
Electronics Engineering Department, American University in Cairo, Cairo, Egypt
Radiation Engineering Department, Egyptian Atomic Energy Authority, Cairo, Egypt
- 1 Faculty of Engineering, Cairo University, Giza, Egypt
- 2 Faculty of Engineering, Cairo University, Giza, Egypt
- 3 College of Computing and Information Technology, Arab Academy for Science, Technology & Maritime Transport, Cairo, Egypt
- 4 Electronics Engineering Department, American University in Cairo, Cairo, Egypt
- 5 Radiation Engineering Department, Egyptian Atomic Energy Authority, Cairo, Egypt
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Abstract
In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.
KeywordsDynamic Power EstimationLogic PicturesCMOS Digital Logic CircuitsToggle RateUnit-Delay Model
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