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Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study
Faculty of Engineering, Cairo University, Cairo, Egypt
Electronics Engineering Department, American University in Cairo, Cairo, Egypt
Radiation Engineering Department, NCRRT, Cairo, Egypt
College of Computing and Information Technology, AASTMT, Cairo, Egypt
- 1 Faculty of Engineering, Cairo University, Cairo, Egypt
- 2 Electronics Engineering Department, American University in Cairo, Cairo, Egypt
- 3 Radiation Engineering Department, NCRRT, Cairo, Egypt
- 4 College of Computing and Information Technology, AASTMT, Cairo, Egypt
Circuits and Systems·Volume 04 (2013)·Pages 364–368·Published 6 August 2013·DOI10.4236/cs.2013.44049
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Abstract
This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set; this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.
KeywordsCurrent Mode Logic (CML)CMOSTestingStuck-At Faults
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