A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter
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Abstract
The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 µm CMOS technology. Active area of chip is 1.37 mm2.
- S. M. Ha, T. K. Nam and K. S. Yoon, “An I/Q Channel 12-bit 120 Ms/s CMOS DAC with Three Stage Thermometer Decod-ers for WLAN,” Proceedings of the IEEE Asia Pacific Confe-rence on Circuits and Systems, Singapore, 4-7 December 2006, pp. 355-358. doi:10.1109/APCCAS.2006.342443
- N. Ghittori, et al., “1.2-V Low-Power Multi-Mode Dac+Filter Blocks for Recon-figurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters,” IEEE Journal of Solid- State Circuits, Vol. 41, No. 9, 2006, pp. 1970-1982. doi:10.1109/JSSC.2006.880602
- S. Khorram, et al., “A Fully Integrated SOC for 802.11 b in 0.18 μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, 2005, pp. 2492-2501. doi:10.1109/JSSC.2005.857419
- S. Mehta, et al., “An 802.11 g WLAN SOC,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, 2005, pp. 2483-2491. doi:10.1109/JSSC.2005.857418
- C. Eklund, R. Marks, K. Stanwood and S. Wang, “IEEE Standard 802.16: A Technical Overview of the Wireless Man Air Interface for Broadband Wireless Access,” IEEE Communications Magazine, Vol. 40, No. 6, 2002, pp. 98-107. doi:10.1109/MCOM.2002.1007415
- N. Ghittori, et al., “An IEEE 802.11 and 802.16 WLAN Wireless Transmitter Baseband Architecture with a 1.2-V, 600-Ms/s, 2.4-mW DAC,” Analog Integrated Circuits and Signal Processing, Vol. 59, No. 3, 2009, pp. 231-242. doi:10.1007/s10470-008-9262-x
- B. Razavi, “Principles of Data Conversion Systems,” Wiley-IEEE Press, New Jersey, 1995.
- P. Hendriks, “Specifying Com-munication DACs,” IEEE Spectrum, Vol. 34, No. 7, 1997, pp. 58-69. doi:10.1109/MSPEC.1997.609817
- Y. Cong and R. Geiger, “Switching Sequence Optimization for Gradient Error Com-pensation in Thermometer-Decoded DAC Arrays,” IEEE Transaction on Circuits and Systems-II, Vol. 47, No. 7, 2000, pp. 585-595. doi:10.1109/82.850417
- C. Lin.and K. Bult, “A 10-bit, 500-Ms/s CMOS DAC in 0.6 mm2,” IEEE Journal of Sol-id-State Circuits, Vol. 33, No. 12, 1998, pp. 1948-1958. doi:10.1109/4.735535
- J. Vandenbussche, et al., “Syste-matic de Sign of High-Accuracy Current-Steering D/A Con-verter Macro Cells for Integrated VLSI Systems,” IEEE Transaction on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 48, No. 3, 2001, pp. 300-309. doi:10.1109/82.924073
- J. Gonzalez and E. Alarcon, “Clock-Jitter Induced Distortion in High-Speed CMOS Switched-Current Segmented Digital to Analog Converters,” International Symposium on Circuits and Systems (ISCAS’01), Sydney, 6-9 May 2001, pp. 1512-1515.