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A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration
Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
- 1 Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
- 2 Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
- 3 Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
- 4 Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
- 5 Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan
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Abstract
A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.
KeywordsAnalog-to-Digital ConvertorSubranging ArchitectureResistor LadderForeground CalibrationOffset Drift
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