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Reliability of High Speed Ultra Low Voltage Differential CMOS Logic
Nanoelectronics System Group, Department of Informatics, Universisty of Oslo, Oslo, Norway
Department of Micro- and Nanosystems Technology, Buskerud & Vestfold University College, Horten, Norway
- 1 Nanoelectronics System Group, Department of Informatics, Universisty of Oslo, Oslo, Norway
- 2 Department of Micro- and Nanosystems Technology, Buskerud & Vestfold University College, Horten, Norway
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Abstract
In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.
KeywordsCMOSDifferentialFloating-GateSemi-Floating-GateKeeperRechargeUltra Low VoltageHigh SpeedMonte-CarloCadenceSTM90 nm
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