A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator
- 1 Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
- 2 Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
- 3 Department of Electrical and Electronics Engineering, Kagoshima University, Kagoshima, Japan
Abstract
A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.
- Alpman, E., Lakdawala, H., Carley, L.R. and Soumyanath, K. (2009) A 1.1 V 50 mW 2.5 GS/s 7 b Time-Interleaved C-2C SAR ADC in 45 nm LP Digital CMOS. IEEE International Solid-State Circuits Conference Digest Technical Papers, San Francisco, 8-12 Feburary 2009, 76-77.
- Yang, J., Naing, T.L. and Brodersen, B. (2009) A 1-GS/s 6-Bit 6.7-mW ADC in 65-nm CMOS. IEEE Custom Integrated Circuits Conference, San Jose, 13-16 September 2009, 287-290.
- Tai, H.-Y., Tsai, P.-Y., Tsai, C.-H. and Chen, H.-S. (2013) A 0.004 mm2 Single-Channel 6-Bit 1.25 GS/s SAR ADC in 40 nm CMOS. IEEE Asian Solid-State Circuits Conference, Singapore, 11-13 November 2013, 277-280.
- Jiang, X.C., Wang, Z.Y. and Chang, M.F. (2003) A 2 GS/s 6 b ADC in 0.18 μm CMOS. IEEE International Solid-State Circuits Conference Digest Technical Papers, San Francisco, 9-13 February 2003, 322-323.
- Shu, Y.-S. (2012) A 6 b 3 GS/s 11 mW Fully Dynamic Flash ADC in 40 nm CMOS with Reduced Number of Comparators. IEEE Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, 13-15 June 2012, 26-27.
- Chen V.H.-C. and Pileggi, L. (2013) An 8.5 mW 5 GS/s 6 b Flash ADC with Dynamic Offset Calibration in 32 nm CMOS SOI. IEEE Symposium on VLSI Circuits Digest of Technical Papers, Kyoto, 12-14 June 2013, C264-C265.
- Miyahara, M., Lin, J., Yoshihara, K. and Matsuzawa, A. (2010) A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 Bit Flash ADC. IEEE Asian Solid-State Circuits Conference, Beijing, 8-10 November 2010, 1-4.
- Lin, J., Mano, I., Miyahara, M. and Matsuzawa, A. (2012) A 0.5 V, 420 MSps, 7-Bit Flash ADC Using All-Digital Time-Domain Delay Interpolation. IEEE International Conference on Electron Devices and Solid State Circuit, Bangkok, 3-5 December 2012, 1-2.
- Plas, G.-V., Decoutere, S. and Donnay, S. (2006) A 0.16 pJ/Conversion-Step 2.5 mW 1.25 GS/s 4 b ADC in a 90 nm Digital CMOS Process. IEEE International Solid-State Circuits Conference Digest Technical Papers, San Francisco, 6-9 February 2006.
- Kim, J.-I., Sung, B.-R.-S., Kim, W. and Ryu, S.-T. (2013) A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS. IEEE Journal of Solid-States Circuits, 48, 1429-1441.
- Kull, L., Toifl, T., Schmatz, M., Francese, P.A., Menolfi, C., Braendli, M., Kossel, M., Morf, T., Andersen, T.-M. and Leblebici, Y. (2013) A 3.1 mW 8 b 1.2 GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE International Solid-State Circuits Conference Digest Technical Papers, San Francisco, 17-21 February 2013, 468-469.