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Design of Low-Voltage, Low-Power FGMOS Based Voltage Buffer, Analog Inverter and Winner-Take-All Analog Signal Processing Circuits
Present Address: Indian Institute of Technology Delhi (IIT-D), New Delhi, India
Present Address: A.K.G. Engineering College, Ghaziabad, India
Present Address: TRAI, New Delhi, India
Netaji Subhas Institute of Technology, New Delhi, India
- 1 Present Address: Indian Institute of Technology Delhi (IIT-D), New Delhi, India
- 2 Present Address: A.K.G. Engineering College, Ghaziabad, India
- 3 Present Address: TRAI, New Delhi, India
- 4 Netaji Subhas Institute of Technology, New Delhi, India
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Abstract
This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated using SPICE in 180 nm CMOS technology with supply voltages of ±1.25 V. The simulation results demonstrate increase in input range for FGMOS based voltage buffer and analog inverter and maximum power dissipation of 0.5 mW, 1.9 mW and 0.429 mW for FGMOS based voltage buffer, analog inverter and WTA circuits, respectively. The proposed circuits are intended to find applications in low voltage, low power consumer electronics.
KeywordsFGMOSVoltage BufferAnalog InverterWinner-Take-All (WTA)Analog Signal Processing Circuits
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