Content Addressable Memory Using Automatic Charge Balancing with Self-Control Mechanism and Master-Slave Match Line Design
- 1 Department of ECE, KCG College of Technology, KCG Nagar, Chennai, India
- 2 Department of ECE, College of Engineering, Guindy, Anna University, Chennai, India
- 3 Department of ECE, College of Engineering, Guindy, Anna University, Chennai, India
Abstract
Content Addressable Memory (CAM) is a type of memory used for high-speed search applications. Due to parallel comparison feature, the CAM memory leads to large power consumption which is caused by frequent pre-charge or discharge of match line. In this paper, CAM for automatic charge balancing with self-control mechanism is proposed to control the voltage swing of ML for reducing the power consumption of CAM. Another technique to reduce the power dissipation is to use MSML, it combines the master-slave architecture with charge minimization technique. Unlike the conventional design, only one match line (ML) is used, whereas in Master-Slave Match Line (MSML) one master ML and several slave MLs are used to reduce the power dissipation in CAM caused by match lines (MLs). Theoretically, the match line (ML) reduces the power consumption up to 50% which is independent of search and match case. The simulation results using Cadence tool of MSML show the reduced power consumption in CAM and modified CAM cell.
- Chang, Y.-J., Liao, Y.-H. and Ruan, S.-J. (2007) Improve CAM Power Efficiency Using Decoupled Match Line Scheme. Proceedings of 2007 Design, Automation & Test in Europe Conference & Exhibition (DATE), Nice, 16-20 April 2007, 1-6. http://dx.doi.org/10.1109/DATE.2007.364585
- Chang, Y.-J. and Liao, Y.-H. (2008) Hybrid-Type CAM Design for Both Power and Performance Efficiency. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16, 965-974. http://dx.doi.org/10.1109/TVLSI.2008.2000595
- Jarollahi, H., Gripon, V., Onizawa, N. and Gross, W.J. (2013) A Low-Power Content-Addressable Memory Based on Clustered-Sparse Networks. Proceedings of IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Washington DC, 5-7 June 2013, 305-308.
- Onizawa, N., Matsunaga, S., Gaudet, V.C., Gross, W.J. and Hanyu, T. (2014) High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Transactions on Circuits and Systems I: Regular Papers, 61, 865-876. http://dx.doi.org/10.1109/TCSI.2013.2283997
- Onizawa, N., Matsunaga, S., Gaudet, V.C., and Hanyu, T. (2012) High Through Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. Proceedings of 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Lyngby, 7-9 May 2012, 41-48.
- Yang, B.-D., Lee, Y.-K., Sung, S.-W., Min, J.-J., Oh, J.-M. and Kang, H.-J. (2011) A Low Power Content Addressable Memory Using Low Swing Search Lines. IEEE Transactions on Circuits and Systems I: Regular Papers, 58, 2849-2858.
- Agarwal, A., Hsu, S., Mathew, S., Anders, M., Kaul, H., Sheikh, F. and Krishnamurthy, R. (2011) A 128 × 128b High-Speed Wide-And Match-Line Content Addressable Memory in 32 nm CMOS. 2011 Proceedings of the IEEE ESSCIRC (ESSCIRC), Helsinki, 12-16 September 2011, 83-86. http://dx.doi.org/10.1109/ESSCIRC.2011.6044920
- Do, A.T., Chen, S., Kong, Z.-H. andYeo, K.S. (2011) A Low-Power CAM with Efficient Power and Delay Trade-Off. IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, 15-18 May 2011, 2573-2576.
- Wang, C.-C., Hsu, C.-H., Huang, C.-C. and Wu, J.-H. (2010) A Self-Disabled Sensing Technique for Content-Ad-a dressable Memories. IEEE Transactions on Circuits and Systems II: Express Briefs, 57, 31-35. http://dx.doi.org/10.1109/TCSII.2009.2037995
- Chen, C.-C., L, H.-Y. and Wang, J.-S. (2005) The Split-Path AND-Type Match Line Scheme for Very High-Speed Content Addressable Memories. Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), Hsinchu, 1-3 November 2005, 525-528. http://dx.doi.org/10.1109/asscc.2005.251793