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NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates
Nanoelectronics Research Group, Department of Informatics, University of Oslo, Oslo, Norway
Nanoelectronics Research Group, Department of Informatics, University of Oslo, Oslo, Norway
Nanoelectronics Research Group, Department of Informatics, University of Oslo, Oslo, Norway
- 1 Nanoelectronics Research Group, Department of Informatics, University of Oslo, Oslo, Norway
- 2 Nanoelectronics Research Group, Department of Informatics, University of Oslo, Oslo, Norway
- 3 Nanoelectronics Research Group, Department of Informatics, University of Oslo, Oslo, Norway
Circuits and Systems·Volume 07 (2016)·Pages 1916–1926·Published 2 June 2016·DOI10.4236/cs.2016.78166
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Abstract
In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.
KeywordsUltra Low Voltage (ULV)Semi-Floating-Gate (SFG)SpeedNOR GateMonte CarloTSMC 90 nmCMOS
- Rabaey, J.M., Chandrakasan, A. and Nikolic, B. (2003) Digital Integrated Circuits: A Design Perspective.
- Harris, D. (2004) Introduction to CMOS VLSI Design—Lecture 9: Circuit Families (Lecture Notes on the Subject). Harvey Mudd College, Claremont.
- Arthurs, A., et al. (2012) Ultra-Low Voltage Digital Circuit Design: A Comparative Study. IEEE Faible Tension Faible Consommation (FTFC), June 2012, 1-4.
- Ijjada, S.R., Ayyanna, G., Reddy, G.S. and Rao, D.V.M. (2011) Performance of Different CMOS Logic Styles for Low Power and High Speed. International Journal of VLSI Design & Communication Systems (VLSICS), 2, No. 2.
- Aguirre-Hernandez, M. and Linares-Aranda, M. (2011) CMOS Full-Adders for Energy-Efficient Arithmetic Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19, 718-721.
- Heald, R. (2000) A Third-Generation SPARC V9 64-b Microprocessor. IEEE Journal of Solid-State Circuits, 35, 1526-1538. http://dx.doi.org/10.1109/4.881196
- Bearden, D.R. (2000) A 780 MHz PowerPC/Sup TM/Microprocessor with Integrated L2 Cache. International Solid-State Circuits Conference, August 2000, 90-91.
- Silberman, J., et al. (1998) A 1.0-GHz Single-Issue 64-Bit Power PC Integer Processor. IEEE Journal of Solid-State Circuits, 33, 1600-1607. http://dx.doi.org/10.1109/4.726542
- Sung, R.J.-H. and Elliott, D.G. (2007) Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines. IEEE Transactions on Circuits and Systems II: Express Briefs, 54, 460-464. http://dx.doi.org/10.1109/TCSII.2007.892212
- Kumar, R. (2001) Interconnect and Noise Immunity Design for Pentium 4 Processor. Intel Technology Journal, Q1, 1-12.
- Kundu, R. and Blanton, R.D. (2003) ATPG for Noise-Induced Switch Failures in Domino Logic. ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), San Jose, CA, 765-768.
- Shibata, T. and Ohmi, T. (1992) A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations. IEEE Transactions on Electron Devices, 39, 1444-1455.
- Mahmood, S.M. and Berg, Y. (2013) Ultra-Low Voltage and High Speed NP Domino Carry Propagation Chain. 2013 IEEE Faible Tension Faible Consommation, Paris, 1-4.
- Mirmotahari, O. and Berg, Y. (2013) Robust Low-Power CMOS Precharge Logic. Proceedings of the 11th Edition of IEEE Faible Tension Faible Consommation, Paris, June.