Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter
- 1 Department of ECE, Hindusthan Institute of Technology, Coimbatore, India
- 2 Department of EEE, SriGuru Institute of Technology, Coimbatore, India
Abstract
Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite Impulse Response (FIR) filter has been designed using efficient multiplier and adder circuits for optimized APT (Area,Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. These compact full adder and half adder structures are incorporated into Wallace Multiplier and Improved Carry-Save Adder. The proposed 16-bit Carry-Save Adder has been improved by splitting into four parallel phases. Consequently the delay of enhanced Carry- Save Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization.
- Parhi, K.K. (1998) VLSI Digital Signal Processing. Wiley, New York.
- Srinivasan, S., et al. (2013) Split-Path Fused Floating Point Multiply Accumulate (FPMAC). IEEE 21st Symposium on Computer Arithmetic, 7-10 April 2013, 17-24. http://dx.doi.org/10.1109/arith.2013.32
- Kharate, A.B. and Gumble, P.R. (2013) VLSI Design and Implementation of Low Power MAC for Digital FIR Filter. International Journal of Electronics Communication and Computer Engineering, 4, REACT-2013.
- Parhami, B. (2010) Computer Arithmetic: Algorithms and Hardware Designs. 2nd Edition, Oxford University Press, New York.
- Ramkumar, B., Kittur, H.M. and Mahesh Kannan, P. (2010) ASIC Implementation of Modified Faster Carry-Save Adder. European Journal of Scientific Research, 42, 53-58.
- Gowrishankar, V., Manoranjitham, D. and Jagadeesh, P. (2013) Efficient FIR Filter Design Using Modified Carry Select Adder & Wallace Tree Multiplier. International Journal of Science, Engineering and Technology Research, 2, 703- 711.
- Kannan, N., Seshadri, R. and Ramakrishnan, S. (2014) Improved Wallace Tree Multiplier Based Direct Fir Structure Using MCM Technique. Proceedings of ICSEM’14-2nd International Conference on Science, Engineering and Management, March 2014.
- Gnanasekaran, M. and Manikandan, M. (2014) Performance of FIR Filter with Wallace Multiplier over FIR Filters with Truncated Multiplier. International Journal of Computer Science and Engineering Communications, 2, 450-455.
- Waters, R.S. and Swartzlander, E.E. (2010) A Reduced Complexity Wallace Multiplier Reduction. IEEE Transactions on Computers, 59, 1134-1137. http://dx.doi.org/10.1109/TC.2010.103
- Kashyap, S. and Maheshwari, M. (2014) Implementation of High Performance Fir Filter Using Low Power Multiplier and Adder. International Journal of Engineering Research and Applications, 4, 177-181.
- Aksoy, L., Lazzari, C., Costa, E., Flores, P. and Monteiro, J. (2013) Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, 498-551. http://dx.doi.org/10.1109/TVLSI.2012.2188917
- Hsiao, S.-F., Zhang Jian, J.-H. and Chen, M.-C. (2013) Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation. IEEE Transactions on Circuits and Systems II: Express Briefs, 60, 287-291. http://dx.doi.org/10.1109/TCSII.2013.2251958