Research ArticleOpen AccessGoogle Scholar indexed
On the Production Testing of Memristor Ratioed Logic (MRL) Gates
Electronics and Communications Engineering, The American University in Cairo, Cairo, Egypt
Radiation Energy Department, Egyptian Atomic Energy Authority, Cairo, Egypt
Electronics and Communications Engineering, The American University in Cairo, Cairo, Egypt
Electronics and Communications Engineering, The American University in Cairo, Cairo, Egypt
College of Computing and Information Technology AASTMT, Cairo, Egypt
- 1 Electronics and Communications Engineering, The American University in Cairo, Cairo, Egypt
- 2 Radiation Energy Department, Egyptian Atomic Energy Authority, Cairo, Egypt
- 3 Electronics and Communications Engineering, The American University in Cairo, Cairo, Egypt
- 4 Electronics and Communications Engineering, The American University in Cairo, Cairo, Egypt
- 5 College of Computing and Information Technology AASTMT, Cairo, Egypt
Circuits and Systems·Volume 07 (2016)·Pages 3016–3025·Published 2 August 2016·DOI10.4236/cs.2016.710257
Copy link · social · email
Abstract
This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. Test escapes may take place while testing faults in the memristors. Therefore, two solutions are proposed to obtain full coverage for the MRL NAND and NOR gates. The first is to apply scaled input voltages and the second is to change the switching threshold of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs.
KeywordsMemristorsMRLProduction TestingFault ModelFault Coverage
- Kvatinsky, S., Wald, N., Satat, G., Weiser, U.C. and Friedman, E.G. (2012) MRL—Memristor Ratioed Logic. Proceedings of the International Cellular Nanoscale Networks and their Applications, Turin, 29-31 August 2012, 1-6.
- Haron, N.Z. and Hamdioui. S. (2008) Why Is CMOS Scaling Coming to an End. Proceedings of the International Design and Test Workshop (IDT), Monastir, 20-22 December 2008, 98-103. http://dx.doi.org/10.1109/idt.2008.4802475
- Chua, L.O. and Kang, S.M. (1971) Memristive Devices and Systems. IEEE Transactions on Circuit Theory, 18, 507- 519. http://dx.doi.org/10.1109/TCT.1971.1083337
- Strukov, D.B., Sinder, G.S., Stewart, D.R. and Williams, S.R. (2008) The Missing Memristor Found. Nature, 453, 80-83. http://dx.doi.org/10.1038/nature06932
- Mazumder, P., Kang, S. and Waser, R. (2012) Mmeristors: Devices, Models and Applications. Proceedings of the IEEE, 100, 1911-1919. http://dx.doi.org/10.1109/JPROC.2012.2190812
- Wu, J. and Choi, M. (2010) Memristor Lookup Table (MLUT)-Based Asynchronous Nanowire Crossbar Architecture. IEEE Conference on Nanotechnology, Seoul, 17-20 August 2010, 1100-1103. http://dx.doi.org/10.1109/nano.2010.5697869
- Haron, N.Z. and Hamdioui, S. (2011) On the Defect Oriented Testing for Hybrid CMOS/Memristor Memory. IEEE Asian Test Symposium, New Delhi, 20-23 November 2011, 353-358. http://dx.doi.org/10.1109/ats.2011.66
- Haron, N.Z. and Hamdioui, S. (2012) DfT Schemes for Resistive Open Defects in RRAMs. Design, Automation and Test in Europe, Dresden, 12-16 March 2012, 799-804. http://dx.doi.org/10.1109/date.2012.6176603
- Hongal, V.A., Kotikalapudi, R., Kim, Y.B. and Choi, M. (2011) A Novel “Divide and Conquer” Testing Technique for Memristor Based Look up Table. IEEE International Midwest Symposium on Circuits and Systems, Seoul, 7-10 August 2011, 1-4.
- Kannan, S., Rajendran, J., Karri, K. and Sinanoglu, O. (2013) Sneak Path Testing of Crossbar-Based Non-Volatile Random Access Memories. IEEE Transactions on Nanotechnology, 12, 413-426. http://dx.doi.org/10.1109/TNANO.2013.2253329
- Chen, Y and Li, J. (2015) Fault Modeling and Testing of 1T1R Memristor Memories. IEEE VLSI Test Symposium, Napa, CA, 27-29 April 2015, 1-6. http://dx.doi.org/10.1109/vts.2015.7116247
- Olbrich, T., Perez, J., Grout, I.A., Richardson, A.M.D. and Ferrer, C. (1996) Defect-Oriented VS Schematic-Level Based Fault Simulation for Mixed-Signal ICs. Proceedings of the International Test Conference, Washington, 20-25 October 1996, 511-520. http://dx.doi.org/10.1109/test.1996.557076