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Area Efficient Sparse Modulo 2<sup>n</sup> - 3 Adder
Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
- 1 Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
- 2 Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
- 3 Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India
Circuits and Systems·Volume 07 (2016)·Pages 4024–4035·Published 28 October 2016·DOI10.4236/cs.2016.712333
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Abstract
This paper presents area efficient architecture of modulo 2 n - 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2 n - 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log 2 n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.
KeywordsResidue Number System (RNS)Parallel Prefix AdderEnd Around Carry (EAC)Sparse Adder
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