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A Modified PFD Based PLL with Frequency Dividers in 0.18-µm CMOS Technology
Department of Electronics and Communication Engineering, Tamil Nadu College of Engineering, Coimbatore, India
Department of Electronics and Communication Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India
- 1 Department of Electronics and Communication Engineering, Tamil Nadu College of Engineering, Coimbatore, India
- 2 Department of Electronics and Communication Engineering, Sri Ramakrishna Institute of Technology, Coimbatore, India
Circuits and Systems·Volume 07 (2016)·Pages 4169–4185·Published 11 November 2016·DOI10.4236/cs.2016.713343
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Abstract
This paper introduces a modified design of CMOS dynamic Phase Frequency Detector (PFD). The proposed PFD circuit (PPFD) is designed, simulated and the results obtained are analyzed. In order to reduce dead zone, internal signal routing is used in the PPFD circuit. To extend, Phase Locked Loop (PLL) is designed and it is verified with two different Frequency Divider (FD) circuits. There is a decrease in area of the PPFD circuit with 16 transistors and dissipates power of 40.8 pW for 1.2 V power supply. The pre-layout simulation result shows that the PPFD circuit has an elimination of a dead zone. Further, it works with the high speed and reduced power operated in the reference frequency of 50 MHz and the feedback frequency up to 4 GHz.
KeywordsPFDDead ZoneVCOPowerPLL
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