Design of DC-DC Converter for Flash Memory IPs
- 1 Department of electronic engineering, Chanwon National University, Changwon , South Korea
- 2 Department of electronic engineering, Chanwon National University, Changwon , South Korea
- 3 Department of electronic engineering, Chanwon National University, Changwon , South Korea
- 4 Department of electronic engineering, Chanwon National University, Changwon , South Korea
- 5 Department of electronic engineering, Chanwon National University, Changwon , South Korea
- 6 Department of electronic engineering, Chanwon National University, Changwon , South Korea
- 7 Department of electronic engineering, Chanwon National University, Changwon , South Korea
- 8 Department of electronic engineering, Chanwon National University, Changwon , South Korea
Abstract
A DC-DC converter for flash memory IPs performing erasing by the FN (Fowler-Nordheim) tunneling and programming by the CHEI (channel hot electron injection) is designed in this paper. For the DC-DC converter for flash memory IPs using a dual voltage of VDD (=1.5V±0.15V)/VRD (=3.1V±0.1V), a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD (=3.1V±0.1V) is a regulated voltage by a voltage regulator with an external voltage of 5V, which is used as the WL activation voltage in the read mode and an input voltage of the charge pump. The designed DC-DC converter outputs positive voltages of VP6V (=6V), VP8V (=8V) and VP9V(=9V); and a negative voltage of VM8V (=-8V) in the write mode.
- F. Xu et al., "Key Design Techniques of A 40ns 16K Bits Embedded EEPROM Memory," Communication, Cir-cuits and System, vol. 2, pp. 1516-1520, June 2004.
- G. S. Cho et al., “Design of a Small-Area Low-Power, and High-Speed 128-KBit EEPROM IP for Touch Screen Controllers,” Journal of KIMIC, vol. 13, no. 12, pp. 2633-2640, Dec. 2009.
- D. H. Kim et al., "Design of an EEPROM for a MCU with the Wide Vol-tage Range," Journal of Semiconductor Technology and Science, vol. 10, no. 4, pp. 316-324, Dec. 2010.
- S. M. Baek et al., "Design of a Small-Area Low-Power, Asynchronous EEPROM for UHF RFID Tag Chips", Journal of KIMIC, vol. 11, no. 12, pp. 2366-2372, Dec. 2007.
- K. I. Kim et al., "Design of Logic Process based 256bit EEPROM IP for RFID Tag Chips and its Measurements", Journal of KIMIC, vol. 14, no. 8, pp. 1868-1876, Aug. 2010.