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Designing a Full Adder Circuit Based on Quasi-Floating Gate
Department of Electrical Engineering, Azad University, South Tehran Branch, Tehran, Iran
Department of Electrical Engineering, Azad University, South Tehran Branch, Tehran, Iran
- 1 Department of Electrical Engineering, Azad University, South Tehran Branch, Tehran, Iran
- 2 Department of Electrical Engineering, Azad University, South Tehran Branch, Tehran, Iran
Energy and Power Engineering·Volume 05 (2013)·Pages 57–63·Published 30 May 2013·DOI10.4236/epe.2013.53B012
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Abstract
Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.
KeywordsFloating Gate TransistorFull Adder CircuitLeakage CurrentQuasi Floating Gate TransistorRefresh Circuit
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