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TDTL Based Frequency Synthesizers with Auto Sensing Technique

¹ College of Engineering, Khalifa University of Science, Technology and Research, Sharjah Campus, Sharjah, UAE
² College of Engineering, Khalifa University of Science, Technology and Research, Sharjah Campus, Sharjah, UAE
³ College of Engineering, Khalifa University of Science, Technology and Research, Sharjah Campus, Sharjah, UAE

International Journal of Communications, Network and System Sciences·Volume 02 (2009)·Pages 330–343·Published 21 August 2009·DOI10.4236/ijcns.2009.25036

Abstract

This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.

KeywordsTime-Delay Tanlock LoopFrequency SynthesizerPhase Lock LoopIndirect Synthesis

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TDTL Based Frequency Synthesizers with Auto Sensing Technique

Abstract

References (21)