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Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

¹ Electronics and Microelectronics Laboratory, Faculty of Sciences, University of Monastir, Monastir, Tunisia.
² Electronics and Microelectronics Laboratory, Faculty of Sciences, University of Monastir, Monastir, Tunisia.
³ Electronics and Microelectronics Laboratory, Faculty of Sciences, University of Monastir, Monastir, Tunisia.
⁴ Electronics and Microelectronics Laboratory, Faculty of Sciences, University of Monastir, Monastir, Tunisia.

Journal of Signal and Information Processing·Volume 03 (2012)·Pages 122–129·Published 28 February 2012·DOI10.4236/jsip.2012.31016

Abstract

The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The windowing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths.

KeywordsLinear Predictive CodingSystem on Programmable ChipFPGACo-Design

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Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

Abstract

References (20)