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Comparative Study and Analysis of Performances among RNS, DBNS, TBNS and MNS for DSP Applications
Neotia Institute of Technology Management and Science, Diamond Harbour, West Bengal, India
Savita Devi Education Trust-Brainware Group of Institutions, North 24 Pgs, West Bengal, India
School of Engineering and Technology, West Bengal University of Technology, Salt Lake, India
School of Engineering and Technology, West Bengal University of Technology, Salt Lake, India
School of Engineering and Technology, West Bengal University of Technology, Salt Lake, India
- 1 Neotia Institute of Technology Management and Science, Diamond Harbour, West Bengal, India
- 2 Savita Devi Education Trust-Brainware Group of Institutions, North 24 Pgs, West Bengal, India
- 3 School of Engineering and Technology, West Bengal University of Technology, Salt Lake, India
- 4 School of Engineering and Technology, West Bengal University of Technology, Salt Lake, India
- 5 School of Engineering and Technology, West Bengal University of Technology, Salt Lake, India
Journal of Signal and Information Processing·Volume 06 (2015)·Pages 49–65·Published 27 March 2015·DOI10.4236/jsip.2015.62005
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Abstract
This paper presents a comparative study of the performances of arithmetic units, based on different number systems like Residue Number System (RNS), Double Base Number System (DBNS), Triple Base Number System (TBNS) and Mixed Number System (MNS) for DSP applications. The performance analysis is carried out in terms of the hardware utilization, timing complexity and efficiency. The arithmetic units based on these number systems were employed in designing various modulation schemes like Binary Frequency Shift Keying (BFSK) modulator/demodulator. The analysis of the performance of the proposed modulator on above mentioned number systems indicates the superiority of other number systems over binary number system.
KeywordsResidue Number System (RNS)Double Base Number System (DBNS)Triple Base Number System (TBNS)Mixed Number System (MNS)Look Up Table (LUT)Digital Signal Processing (DSP)
- Chiang, C.-L. and Johnsson, L. (1983) Residue Arithmetic and VLSI. IEEE International Conference on Computer Design: VLSI in Computers (ICCCD’83), New York, 31 October-3 November 1983, 80-83.
- Abdelfattah, O. (2011) Data Conversion in Residue Number System. Department of Electrical & Computer Engineering, McGill University, Montreal.
- Dimitrov, V.S., Jullien, G.A. and Miller, W.C. (1999) Theory and Application of the Double-Base Number System. IEEE Transactions on Computers, 48, 1098-1106. http://dx.doi.org/10.1109/12.805158
- Dimitrov, V.S., Sadeghi-Emamchaie, S., Jullien, G.A. and Miller, W.C. (1996) Near Canonic Double-Based Number System (DBNS) with Application in Digital Signal Processing. Proceedings SPIE Conference on Advanced Signal Processing, 4 August 1996, 14-25. http://dx.doi.org/10.1117/12.255433
- Eskritt, J., Muscedere, R., Jullien, G.A., Dimitrov, V.S. and Miller, W.C. (2000) A 2-Digit DBNS Filter Architecture. IEEE Workshop on Signal Processing Systems, Lafayette, 11-13 October 2000, 447-456.http://dx.doi.org/10.1109/SIPS.2000.886743
- Jullien, G.A., Dimitrov, V.S., Li, B., Miller, W.C., Lee, A. and Ahmadi, M. (1999) A Htbrid DBNS Processor for DSP Computation. Proceedings International Symposium on circuits and Systems, ISCAS’99, July 1999, 5-8.
- Chakraborty, A. and Sinha, A. (2011) Conversion of Binary to Single-Term Triple Base Numbers of DSP Applications. ACM SIGARCH Computer Architecture News, 39, 5-11.
- Maitra, S. and Sinha, A. (2007) A Single Digit Triple Base Number System—A New Concept for Implementing High Performance Multiplier Unit for DSP Applications. 6th international Conference on Information, Communications & Signal Processing, Singapore, 2007, 1.
- Ghosh, A., Singha, S. and Sinha, A. (2010) A Novel Architecture of Mixed Number System MAC Unit for Digital signal Processors. International Journal of computer Science and Communication (IJCSC), 1, 175-179.
- Ghosh, A., Singha, S. and Sinha, A. (2012) A New Architecture for FPGA Implementation of a MAC Unit for Digital signal Processors using Mixed number System. ACM SIGARCH Computer Architecture News, 40, 33-38.http://dx.doi.org/10.1145/2234336.2234342
- Kundu, P.P., Bandyopadhyay, O. and Sinha, A. (2008) An Efficient Architecture of RNS Based Wallace Tree Multiplier for DSP Application. IEEE, Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on IEEE, 2008, 221-224.