In this study, a comparison of 5 nm PDSOI and FDSOI n-MOSFETs with SiO 2 and high-k gate dielectrics is carried out using Silvaco TCAD ATLAS platform with necessary models. SOI architectures (PDSOI/FDSOI) offer enhanced electrostatic control compared to bulk CMOS, which suffers from threshold instability, SCEs and leakage near the 20 nm node. In this scaling, various high-k dielectric materials were explored for gate oxide. Among those, Ta 2 O 5 shows comparatively much better results with respect to the optimized SiO 2 -gated device of the same SOI architecture. The PDSOI device showed 39.15% lower Threshold Voltage (V th ), 26.5% improved Subthreshold-Swing (SS), leakage current (I OFF ) of 2.17 × 10 − 10 A, and I ON /I OFF ratio of 1.64 × 10 6 , making it suitable for analog and near-threshold logic applications. The FDSOI device exhibited closely unchanged V th of 0.6604 V, 34% improved SS, ultra-low I OFF of 1.69 × 10 − 13 A and I ON /I OFF ratio 7.41 × 10 9 favoring use in high-speed and ultra-low-leakage digital systems. This paper gives valuable insight and guidelines for selecting optimal SOI architectures and gate dielectric materials in future ultra-scaled, energy-efficient, and high-performance integrated circuits.
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