Research ArticleOpen AccessGoogle Scholar indexed
Simulation Study of Nanoscale FDSOI MOSFET Characteristics
Department of Electrical & Electronic Engineering, Ahsanullah University of Science & Technology, Dhaka, Bangladesh
- 1 Department of Electrical & Electronic Engineering, Ahsanullah University of Science & Technology, Dhaka, Bangladesh
Soft Nanoscience Letters·Volume 13 (2023)·Pages 13–22·Published 18 July 2023·DOI10.4236/snl.2023.133002
Copy link · social · email
Abstract
Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.
KeywordsFully DepletedSilicon on InsulatorThreshold VoltageSubthreshold SlopeLeakage CurrentGate Length
- Semiconductor Industry Association (2015) 2015 International Technology Roadmap for Semiconductors (ITRS). https://www.semiconductors.org/resources/2015-international-technology-roadmap-for-semiconductors-itrs/
- Cheng, K. and Khakifirooz, A. (2016) Fully Depleted SOI (FDSOI) Technology. Science China Information Sciences, 59, Article No. 061402. https://doi.org/10.1007/s11432-016-5561-5
- Shin, C., Cho, M.H., Tsukamoto, Y., Nguyen, B.Y., Mazure, C., Nikolic, B. and Liu, T.J.K. (2010) Performance and Area Scaling Benefits of FDSOI Technology for 6-T SRAM Cells at the 22-nm Node. IEEE Transactions on Electron Devices, 57, 1301-1309. https://doi.org/10.1109/TED.2010.2046070
- Chouksey, S., Fossum, J.G. and Agrawal, S. (2010) Insights on Design and Scalability of Thin-BOX FD/SOI CMOS. IEEE Transactions on Electron Devices, 57, 2073-2079. https://doi.org/10.1109/TED.2010.2052420
- Xu, N., et al. (2012) Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs. IEEE Electron Device Letters, 33, 318-320. https://doi.org/10.1109/LED.2011.2179113
- Theodorou, C.G., et al. (2014) Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs. IEEE Transactions on Electron Devices, 61, 1161-1167. https://doi.org/10.1109/TED.2014.2307201
- Musalgaonkar, G., Sahay, S., Saxena, R.S. and Kumar, M.J. (2019) A Line Tunneling Field-Effect Transistor Based on Misaligned Core—Shell Gate Architecture in Emerging Nanotube FETs. IEEE Transactions on Electron Devices, 66, 2809-2816. https://doi.org/10.1109/TED.2019.2910156
- Mishra, V.K. and Chauhan, R.K. (2018) Efficient Layout Design of Junctionless Transistor Based 6-T SRAM Cell using SOI Technology. ECS Journal of Solid State Science and Technology, 7, 456-461. https://doi.org/10.1149/2.0061809jss
- Mishra, V.K. and Chauhan, R.K. (2018) Area Efficient Layout Design of CMOS Circuit for High-Density ICs. International Journal of Electronics, 105, 73-87. https://doi.org/10.1080/00207217.2017.1340978
- Kumar, M.J. and Siva, M. (2008) The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs. IEEE Transactions on Electron Devices, 55, 1554-1557. https://doi.org/10.1109/TED.2008.922859
- Silvaco International (2004) ATLAS User’s Manual Device Simulation Software. Santa Clara.
- Verma, A., Mishra, A., Singh, A. and Agrawal, A. (2014) Effect of Threshold Voltage on Various CMOS Performance Parameter. International Journal of Engineering Research and Applications, 4, 21-28.