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Design of Low Power and High Speed CMOS Comparator for A/D Converter Application
Department of Electronics & Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, India
Department of Electronics & Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, India
- 1 Department of Electronics & Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, India
- 2 Department of Electronics & Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, India
Wireless Engineering and Technology·Volume 03 (2012)·Pages 90–95·Published 28 April 2012·DOI10.4236/wet.2012.32015
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Abstract
This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.
KeywordsCMOS ComparatoLow PowerHigh SpeedSigma-Delta ADC and Cadence
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